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25A512
2.10
CHIP ERASE
The CHIP ERASE instruction will erase all bits (FFh) in
the array. A Write Enable ( WREN ) instruction must be
given prior to executing a CHIP ERASE . This is done
by setting CS low and then clocking out the proper
instruction into the 25A512. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch.
The CHIP ERASE instruction is entered by driving the
CS low, followed by the instruction code (Figure 2-10)
onto the SI line.
The CS pin must be driven high after the eighth bit of
the instruction code has been given or the CHIP
ERASE instruction will not be executed. Once the CS
pin is driven high the self-timed CHIP ERASE instruc-
tion begins. While the device is executing the CHIP
ERASE instruction the WIP bit in the STATUS register
can be read to determine when the CHIP ERASE
instruction is complete.
The CHIP ERASE instruction is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning ?,
?, or all of the array is protected.
FIGURE 2-10:
CHIP ERASE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
1
1
0
0
0
1
1
1
High-Impedance
SO
? 2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 17
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